RISC-V Reddit

24 March 2024 17:24

Made a programmable RISCV-32I core in Verilog

I designed this core primarily as a fun side project.

I decided to spread a word here in case anyone is interested.

I would love to receive feedback on whether such a project could prove useful to our community and for future expansions to include.

PYGMY

Thanks, :)

P.S.1 I don't know whether the Advice/Help flair is the correct tag to use but this seemed right at the moment. If not I could delete the post and re upload it using another tag.

P.S.2 If such posts do not belong to this sub, please inform me in the comments to delete it asap.

https://redd.it/1bmok7m
@r_riscv

RISC-V Reddit

23 March 2024 07:24

Market share stats?

Are there any statistics on RISC-V's position in different market segments relative to other platforms? I'm assuming it would be difficult to get super accurate stats because of weird edge cases like replacing proprietary, in-house chips in hard drives. But I'd love to be able to track it's market share over time.

https://redd.it/1blkses
@r_riscv

RISC-V Reddit

22 March 2024 21:24

China-made RISC-V PCIe 5.0 SSD controller promises competitive performance — up to 14.2 GB/s without a fan
https://www.tomshardware.com/pc-components/ssds/china-made-risc-v-pcie-50-ssd-controller-promises-competitive-performance-up-to-142-gbs-without-a-fan

https://redd.it/1bl8goc
@r_riscv

RISC-V Reddit

22 March 2024 19:24

How to implement communication between the host and simulated RISCV core in Spike?

Hello,

I am using Spike and I am looking for a way to allow communication between the host and the simulated core. I understand that the "RISC-V Frontend Server" (FESVR) exists for this purpose, but I am unable to find any information on how it works or how to use the header files that are installed with Spike.

There's also MMIO device plugins, which allow for shared memory between the host and the target machine. This seems to work, but only with bare-metal assembly code. I was wondering if there is a way to use this with the proxy kernel (trying to access the memory location of the loaded device will cause a segfault).

If anyone can share information about this I would really appreciate it. I am totally lost and it doesn't seem like there is very much material on Spike available on the internet.

https://redd.it/1bl4zjt
@r_riscv

RISC-V Reddit

22 March 2024 15:24

user input in risc-v

im attempting to ask the user to input two numbers in risc-v and the program then computes and prints their sum, difference, product, and quotient each on a new line. I cannot get the I/O part of RARS to allow me to input data? any tips?

https://redd.it/1bl08on
@r_riscv

RISC-V Reddit

22 March 2024 10:24

SG2042 Newsletter (2024-03-22 #034)

## Editor's Note

Welcome to the thirty-fourth issue of the SG2042 Newsletter. In this issue, we will bring you a series of exciting content about the second Xuantie RISC-V Ecosystem Conference.

## Highlights

+ On March 14, 2024, the second Xuantie RISC-V Ecosystem Conference was grandly opened in Shenzhen! SOPHGO showcased its full stack of RISC-V products and solutions at the conference. Peng Gao, Senior Vice President of SOPHGO, delivered a speech on "Reshaping Computing Power, Leading the Productivity Revolution." In his speech, Peng Gao shared that in today's era, where large models lead a new revolution in productivity, the industry urgently requires more economical computing resources and a more efficient computing power scheduling mechanism. Leveraging the open, universal, and free RISC-V technology, SOPHGO is committed to reshaping the boundaries of computing power and leading a new revolution in productivity.

Related news

## Upstream

Most of the code is already open-source and can be obtained from repositories such as github.com/SOPHGO. The following are some useful repo resources:

### Linux kernel

+ Sophgo Community work: https://github.com/sophgo/linux-riscv

+ System optimization

+ Linux Official Community Upstream work:

+ 6.9 enters the second week of the merge window, the driver/bindings part of the reset driver has been merged.

### U-Boot

https://github.com/sophgo/u-boot/tree/sg2042-dev

+ No commits this week

### OpenSBI

https://github.com/sophgo/opensbi/tree/sg2042-dev

+ No commits this week

## Case Study

We're looking for fun, good, or profitable use cases for SG2042. Feel free to share your experiences with us - just send a PR!

## Events and Games

+ The 19th China Graduate Student Electronic Design Contest | SOPHGO Cup | Prizes are Waiting for you!event-1

event-1:https://mp.weixin.qq.com/s/gkNs5lia9oN7xNflkLv2Lg

## In the News

+ Milk-V Duo + MAX98357A = Audio Outputnews-1
+ MMDVM Hotspot Box controlled by Milk-V Duonews-2
+ Connect to Wi-Fi on Duo Snews-3
+ RISC-V and Milk-V Fusion: A Pocket-Sized Computing Powerhouse for Embedded Applicationsnews-4

news-1:https://www.youtube.com/shorts/Ze7ocYdTn38
news-2:https://community.milkv.io/t/milkv-duo-mmdvm/1568
news-3:https://community.milkv.io/t/connect-to-wi-fi-on-duo-s/1540
news-4:https://www.youtube.com/watch?v=aZeQb3kLM0c

### News from Japanese, Korean and other language communities

Not ready yet. We are recruiting multilingual volunteers and interns. Welcome to join us! Please email Wei Wu if you are interested in being an open source community intern.

https://redd.it/1bkuhfv
@r_riscv

RISC-V Reddit

22 March 2024 01:24

Anybody has a working VF2 Debian stable or sid setup?

I did some research before buying, saw the usual warnings about having to update firmware, that’s not bad, right? The JH7110 Upstream Status page looked promising so I went ahead and ordered the 8GB version.

Oh boy is this thing hard to get working. Updated to the latest firmware (v5.11.3). The best image I could find is https://github.com/yuzibo/vf2-debian-image since thomasdstewart/starfive-visionfive2 is broken. Unfortunately it seems that StarFive broke the generic U-boot in their firmware since last summer and yuzibo’s image fails to boot, see https://github.com/starfive-tech/VisionFive2/issues/87 (it’s the exact same errors, this seems to a common issue and easy to reproduce). Maybe I need to compile my own U-Boot but I hope not because I’ve seen a lot of people struggle with that. I tried to fix the U-Boot environment manually but it’s a real mess.

If I manually load DTB, vmlinuz and initrf, then set bootargs in env (had to replace root with my root partition, the UUID in yuzibo’s image fails to boot) and manually execute ”booti ${kerneladdrr} ${ramdiskaddrr}:${filesize} ${fdtaddrr}” I can get it to boot. Only with the bundled DTB though, DTB in latest firmware release panics on boot. With 8GB VF2 only 4GB of RAM is available (probably need to decompile and edit DTB) and HDMI doesn’t work. And unfortunately the system locks up for 10 seconds every second time I run a command (with both UART and SSH, tried debugging why that happens but it’s too painful with it constantly freezing, the usual suspects like hosts file and DNS did not help), it uses some weird DNS setup by default and so on. Not exactly the experience I was looking forward to.

Ubuntu Server won’t boot either, erasing and reverting U-Boot env vars to default does not help. And it does not have HDMI support AFAIK.

It seems there are no official guidelines for the boot flow by StarFive so everyone just follows what the official StarFive images do, then they change change the official firmware to enable some new feature for their snapshot images and break things for everyone else. This is sad because VF2 has so much potential and currently is the best RISC-V SBC available but it seems it’s really hard to enjoy this new open ISA unless you choose to use their snapshot images which are outdated, closed and you can’t even apt-get upgrade without breaking it. And which come with huge non-reproducible binary blobs easy to compromise without anyone noticing.

If you have a working setup please share it with us and show that it’s just me being dumb and there’s nothing wrong with VF2 ;-) Vanilla Debian is something that usually works everywhere, there’s no excuse for StarFive not to support it without everyone having to figure things out by themselves, patch, custom build etc. I don’t need 3D accel, NVMe, WiFi or anything like that. Just the bare minimum - framebuffer, Ethernet, SD card, USB.


https://redd.it/1bkksy7
@r_riscv

RISC-V Reddit

21 March 2024 07:24

RiscV 6th edition

Where can I get softcopy of David A patterson , John L hennessy RISC 6th edition
I have 5th edition

https://redd.it/1bjzkvc
@r_riscv

RISC-V Reddit

20 March 2024 19:24

DietPi released a new version 9.2

DietPi is a lightweight Debian based Linux distribution for SBCs and server systems, with the option to install desktop environments, too. It ships as minimal image but allows to install complete and ready-to-use software stacks with a set of console based shell dialogs and scripts.


The source code is hosted on GitHub: [https://github.com/MichaIng/DietPi](https://github.com/MichaIng/DietPi)
The main website can be found at: [https://dietpi.com/](https://dietpi.com/)
Wikipedia: [https://de.wikipedia.org/wiki/DietPi](https://de.wikipedia.org/wiki/DietPi)


The project released the new version DietPi v9.2 on March 16th, 2024.


The highlights of this version are:

* **NanoPi R4S:** Improvements for ethernet ports
* **DietPi-Banner:** Option for RAM usage display added
* **Gogs/Gitea:** Improvements on user repositories via SSH
* **DietPi-Config**: Stabilization for WiFi connection and for audio
* Fixes for **PaperMC, Nextcloud, Home Assistant, IceCast/DarkIce, LXQt**

The full release notes can be found at: [https://dietpi.com/docs/releases/v9\_2/](https://dietpi.com/docs/releases/v9_2)

https://redd.it/1bjizwt
@r_riscv

RISC-V Reddit

20 March 2024 08:24

What’s the best way to learn RARS?

Do you know any websites or textbooks that helped you out during your journey of learning how to program in RARS for RISC V? I’m currently in a bachelor degree in CS and I’m really worried about CA because the first part about sequentially logic wasn’t really clear to me and I wanna get going and starting applying seriously.

https://redd.it/1bj7ldt
@r_riscv

RISC-V Reddit

19 March 2024 23:24

Having hard time trying to work on CH32V307

Hi,

I've purchased a development board to try out the CH32V307 MCU.

I was planning to use my environment of choice aka vim, openocd and (c)make and felt like this device is total nightmare.

First of all, near to impossible to get openocd working. I've looked over the internet and saw various "copies" of WCH/mounriver's openocd fork and was unable to build on my Mac (various compiler error). Fortunately I've managed to patch this fork just few lines and got it built. But then, no mention of any configuration file to be used so I've dig a bit more and found several ones including one shipped with the AUR package.

Connected the board to my Mac (also tried on my thinkpad, running Arch) and it both case I got the same result:

riscv-openocd-wch -f ~/Dev/aur/riscv-openocd-wch/wch-riscv.cfg 
Open On-Chip Debugger 0.11.0+dev-g395b49ca4-dirty (2024-03-19-21:35)
Licensed under GNU GPL v2
For bug reports, read
 http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Error: unknow WCH-LINK 

RISC-V Reddit

19 March 2024 13:24

Damo Academy plans to launch latest RISC-V chip this year as chip demand grows
https://www.scmp.com/tech/big-tech/article/3255830/alibabas-damo-academy-plans-launch-latest-version-its-xuantie-risc-v-processor-year

https://redd.it/1biimbm
@r_riscv

RISC-V Reddit

18 March 2024 21:24

What's the purpose of SLT/SLTI?

I've been reading about the RISCV ISA and everything in the core seems to have a place, but I was surprised about the SLT instructions. I understand what they do, but I can't imagine that's something that compilers works often generate, and it seems easy to get the same result with a few instructions of you every need it.

The use case I imagine is whenever you use comparisons as book values to be stored (rather than jump conditions), with those booleans encoded as 0/1 as C does. Are there any other important use cases that I'm missing that are made easier with SLT?

https://redd.it/1bi03h4
@r_riscv

RISC-V Reddit

18 March 2024 15:24

PineVox virtual assistant with BL606P
https://pine64.org/2024/03/17/march-update-making-waves/#pinevox---virtual-assistant

https://redd.it/1bhr2ob
@r_riscv

RISC-V Reddit

16 March 2024 09:24

Banana Pi BPI-F3 SpacemiT K1 RISC-V chip datasheet

Banana Pi BPI-F3 SpacemiT K1 RISC-V chip datasheet

​

https://preview.redd.it/mbq84mxclnoc1.png?width=817&format=png&auto=webp&s=4b08cc4d4755b948145022c7f7f7e08ea27931a4

https://docs.banana-pi.org/en/BPI-F3/SpacemiT\_K1\_datasheet

\#SpacemiT \#K1 \#riscv \#bananapi \#raspberrypi \#iot \#Industrialcontrol \#network \#EdgeComputing

https://redd.it/1bg13in
@r_riscv

RISC-V Reddit

23 March 2024 15:24

Could anyone please confirm if SWIO of Chlink-E is 5v tolerant?

Hello!
The reason I ask is ch32v003 can be powered from a 5V supply. Is it safe for my programmer to flash/debug a chip powered from a 5v rail? (provided that the pin (soic-8 package here) is not used for any other function)

https://redd.it/1bltc1s
@r_riscv

RISC-V Reddit

23 March 2024 00:24

Linux 6.9 Adds New RISC-V Vector-Accelerated Crypto Routines
https://www.phoronix.com/news/Linux-6.9-RISC-V

https://redd.it/1bld7d2
@r_riscv

RISC-V Reddit

22 March 2024 20:24

How to implement communication between the host and simulated RISCV core in Spike?

Hello,

I am using Spike and I am looking for a way to allow communication between the host and the simulated core. I understand that the "RISC-V Frontend Server" (FESVR) exists for this purpose, but I am unable to find any information on how it works or how to use the header files that are installed with Spike.

There's also MMIO device plugins, which allow for shared memory between the host and the target machine. This seems to work, but only with bare-metal assembly code. I was wondering if there is a way to use this with the proxy kernel (trying to access the memory location of the loaded device will cause a segfault).

If anyone can share information about this I would really appreciate it. I am totally lost and it doesn't seem like there is very much material on Spike available on the internet.

https://redd.it/1bl4zjt
@r_riscv

RISC-V Reddit

22 March 2024 17:24

Good alternative to the SparkFun RED-V RedBoard - SiFive RISC-V FE310 SoC v

Hello, I am an absolute beginner in the field of Risc-V. The lectures at university refer to the SparkFun board mentioned above, so I wanted to buy one.

Unfortunately, the boards are no longer manufactured and are sold out everywhere. Does anyone here know of any good alternatives that are not too different?

https://redd.it/1bl1vjd
@r_riscv

RISC-V Reddit

22 March 2024 11:24

Efinity Titanium Ti375 FPGA offers quad-core hardened RISC-V block, PCIe Gen 4, 10GbE
https://www.cnx-software.com/2024/03/22/efinity-titanium-ti375-fpga-offers-quad-core-hardened-risc-v-block-pcie-gen-4-10gbe/

https://redd.it/1bkvaa6
@r_riscv

RISC-V Reddit

22 March 2024 04:24

is there any board with displayport?

I haven't seen any boards with displayport. Is there any reason for that? Isn't it supposed to be cheaper to add a display port because it's royalty free? Or is it something technical?

https://redd.it/1bkpeat
@r_riscv

RISC-V Reddit

21 March 2024 10:24

Alibaba claims it will launch a server-grade RISC-V processor this year
https://www.tomshardware.com/pc-components/cpus/alibaba-claims-it-will-launch-a-server-grade-risc-v-processor-this-year

https://redd.it/1bk2fbc
@r_riscv

RISC-V Reddit

21 March 2024 04:24

The RVV github has been archived and made read-only

So there will be no further updates made to https://github.com/riscv/riscv-v-spec and presumably work on RVV 2.0 will be done in a new repo.

I just got in one final comment on my April 2021 Issue #667 raised seven months before RVV 1.0 was ratified, asking (fruitlessly) for a couple of unnecessary incompatibilities with 0.7.1 to be changed.

/u/camel-cdr-'s PR trying to make the README less confusing didn't get in.

I've taken the liberty of forking the repo, creating branches for 0.7.1 and 1.0, and updating the README in each branch to be (hopefully) more informative.

1.0: https://github.com/brucehoult/riscv-v-spec/

0.7.1: https://github.com/brucehoult/riscv-v-spec/tree/0.7.1

https://redd.it/1bjvsmx
@r_riscv

RISC-V Reddit

20 March 2024 12:24

Banana Pi BPI-F3 SpacemiT K1 8 core RISC-V chip run OpenWRT,
https://youtube.com/watch?v=ejV5KFww8Xo&si=2VQTJs3FaPVOdksv

https://redd.it/1bjaaup
@r_riscv

RISC-V Reddit

20 March 2024 02:24

How to do bare metal in Milk V Duo?

Hey, I was wondering how to write a bare metal application for milk v duo.

I am not talking about FreeRTOS or Arduino for the second core. I want to toss Linux aside and run my application/OS on the big core.

I posted my question on the official community but didn't get any response https://community.milkv.io/t/how-to-run-executable-on-the-duo-from-sd-card/1553

I also tried following the examples on OSDev but my program doesn't run

https://wiki.osdev.org/RISC-V\_Bare\_Bones

For a hello world, I am trying to run a simple blinky program.

Thanks in advance

https://redd.it/1bj0gcc
@r_riscv

RISC-V Reddit

19 March 2024 14:24

How to benchmark Risc V core (such as shakti E class) using "coreMark".

I am currently strategizing the benchmarking process for the RISC-V core. During my research, I encountered references to "coreMark". However, I am struggling to locate comprehensive guidance on their utilization. I would greatly appreciate detailed instructions on how to do it.

https://redd.it/1bik2bl
@r_riscv

RISC-V Reddit

19 March 2024 11:24

TinyVision is a compact Allwinner V851S/V851S3-powered Linux board for vision-based applications
https://www.cnx-software.com/2024/03/19/tinyvision-compact-allwinner-v851s-v851s3-powered-linux-board-vision-based-applications/

https://redd.it/1big6si
@r_riscv

RISC-V Reddit

18 March 2024 18:24

How to benchmark Risc V core (such as shakti E class) using codemarks.

I am currently strategizing the benchmarking process for the RISC-V core. During my research, I encountered references to codemarks. However, I am struggling to locate comprehensive guidance on their utilization. I would greatly appreciate detailed instructions on how to do it.

https://redd.it/1bhw5eh
@r_riscv

RISC-V Reddit

17 March 2024 02:24

Milk-V Pioneer owners: how is your experience?

Sooo .. it's several months since the pre-ordered Pioneers arrived at their new owners. And they've been available for immediate delivery if someone orders one now.

So how are they? Should people buy them?

I haven't seen a lot of owner reviews. Or any. I know there are people in this forum who bought them.

Are all y'all just quietly enjoying them, or there are problems that you're kind of embarrassed and annoyed about and hoping/waiting to get fixed?

I love my VisionFive 2 and LicheePi 4A boards for testing things on real hardware, and for big native RISC-V builds and other work (e.g. running thousands of unit tests) RISC-V Ubuntu running in docker on my 32 core (64 T) ThreadRipper or 24 core (32 T) i9-13900HX laptop work very well -- each process gets a new qemu-user, which has a certain start-up overhead but can use allll the cores efficiently.

But 64 C910 cores should beat out 24 or 32 x86 cores running qemu. By a lot. If you use all or most of them. So it's tempting.

So, Pioneer owners ... regrets, or no regrets?

https://redd.it/1bgkelm
@r_riscv

RISC-V Reddit

16 March 2024 05:24

4,000,000,000,000 Transistors, One Giant Chip (Cerebras WSE-3)
https://m.youtube.com/watch?v=f4Dly8I8lMY

https://redd.it/1bfxgok
@r_riscv